http://blog.corensic.com/2011/11/28/virtual-machines-memory/ →
Great article describing how virtual->physical address translation works in x86.
Summary
- Each process gets its own private page table. The pointer to this page table will be stored in a special CR3 register upon a context-switch.
- Walking the private page tables is expensive. So the entries are cached in a TLB. But that means during a context-switch, you’d to flush the entire TLB cache.
- Newer AMD and Intel CPUs, apparently attach a Address-Space Identifier (ASID) to every TLB entry. That way no invalidation is required; you just skip the entries in the TLB with ASIDs that don’t match the ASID corresponding to the currently running process.
The author has another article explaining how this works when you’re running virtualized operating systems on top of a hypervisor.
